謝旻言, Min-Yan(Ian) Hsieh

Digital Design Engineer and Digital Verification(DV) Engineer

Analog Design Engineer

Quantitative Developer

Software Engineer

with 1+ years experience

I am a passionate and versatile engineer with a strong foundation in Electrical Engineering, Computer Science, and Quantitative Finance. My journey has taken me through a wide range of domains — from circuit design to system optimization — allowing me to develop a deep, cross-disciplinary skill set.

My core expertise includes:

Analog and mixed-signal circuit design

Digital IC and SoC design and verification

Computer architecture and compiler fundamentals

High-speed interface protocols (e.g., PCIe, MIPI, UCIe, DDR5, USB4.0)

Hardware-software co-development and system-level integration

AI, machine learning, and computer vision applications

Performance optimization in real-time systems and trading platforms

Currently, I work as a DV Engineer at NVIDIA, where I focus on the design and verification of high-performance chips. My role involves not only verification methodologies but also design insights and system-level thinking, aligning closely with architectural development and performance analysis.

I enjoy working at the intersection of hardware, software, and intelligent systems — where innovation happens. My goal is to continue expanding my knowledge in chip architecture, system integration, and computational finance, contributing to technologies that shape the future.

Education

National Yang Ming Chiao Tung University, Department of Electrical and Electronics Engineering (2022/09~NOW)

Master Degree of Electrical and Electronics Engineering,

Research Area is Analog and Mix-signal Circuit Design, Phase-Locked Loops, Analog-to-Digital Converters

National Yang Ming Chiao Tung University, Electrical and Computer Engineering (2022/09~NOW)

Bachelor Degree of Electrical and Computer Engineering

Work Experience

NVIDIA, Design Verification Engineer (2025/04~Now)

Proficient in digital design and verification, with hands-on experience in SystemVerilog and UVM for developing scalable and reusable verification environments
Contributed to Audio SoC architecture verification, including testbench development, module-level verification, and automation of verification flows
Led the build-up of verification platforms, improving coverage and efficiency through modular and configurable test infrastructure
Participated in the development of AI-driven EDA tools, leveraging Python and C/C++ to integrate machine learning techniques into design automation workflows

VICI Holdings, FPGA Engineer (2024/09~now)

Altera FPGA, Quartus, Xilinx FPGA, Vivado, Verilog, Systemverilog, Peryl, Exchange API, Digital Design, Design Verification, C/C++
Implementation of Low-Latency Trading Infrastructure based on FPGA and high performance software, reducing execution time by 50%
Low-Latency DDR4 and HBM Memory Controller realization
Utilizing PCIe to complete a high-speed trading system
Construction of high performance trading strategy and risk control algorithm

Taiwan Electronic System Design Automation (TESDA) Silicon Engineer (2023/06~2024/06)

UVM, Test Plan, Design Verfication, Computer Architecture, Compilter Design, RISCV, DLA, GPU, AHB, AXI, PCIe, MIPI, DDR5
ESL and DFT Design, RISC-V CPU and SoC Design Verification
NPU, APU and Deep Learning Accelerator(DLA) Development and Verification
AMBA Protocol and SPI, UART, I2C, JTAG, PCIe, MIPI, UCIe and DDR5
IP-XACT, Parser, Compiler and algorithm design

Internship

Mediatek, Summer Intern (2024/07~2024/08)

TDC for SRAM readout speed measurement in 2nm process
Low Power and high performance SRAM circuit Design
Automatic testing for SRAM using SPICE, Peryl, and script

Industrial Technology Research Institute (ITRI)(2023/05~2022/06)

Python, Pytorch, Tensorflow, Machine Learning, Deep Learning
Use Deep Learning technique to realize face and commodity detection
Image recognition to fulfill the unmanned store

Richtek Summer Internship (2022/07~2022/08)

HSPICE, Finesim, Virtuoso, Spectre, Oscilloscope, Hall Transducer
Two-stage OP, Folded-cascoded OP, LDO analysis and simulation with advanced process
Oscillator and bandgap reference circuit analysis

Honor

High School Physics Science Fair Excellence

Conducted research on the generation of electricity through water flow across hydrophobic surfaces

First place in the TRML Mathematics

Competition

Investigated and demonstrated proficiency in high school and even university-level mathematics, including algebra, geometry, probability, and other domains. Achieved the top-ranking nationwide in these subjects.

Certificate of Selection to the International Physics Olympiad Team

Due to outstanding performance in the preliminary rounds, you are invited to join the national team as a representative

Invitation Letter for AIME Participant

Due to achieving a competition ranking in the top 3.5% nationally in the AMC 10, you are invited to participate in the American Invitational Mathematics Examination (AIME)

WorldQuant Challenge Gold Ceritificate

Earned Gold Level certification in the WorldQuant Challenge, an international competition focused on quantitative finance. Developed profitable quantitative trading strategies by engineering alpha factors and optimizing portfolios

MediaTek Summer Internship

MediaTek Summer Internship Certificate at Platform Technology Design(PTD), Memory Circuit Design(MCD) team. The primary focus is on low-noise TDC circuit implementation and high-performance SRAM circuit design.

Goole HPS Certificate

Designing a smart refrigerator management system through hardware system design, frontend and backend software development, and machine learning for computer vision recognition.

Certificate

Practical Certificate in RF IC Design

Validates skills in designing Radio Frequency Integrated Circuits (RF ICs), covering principles, mixed-signal integration, and testing techniques, essential for roles in related industries.

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