A person passionate about groundbreaking developments in science, technology, semiconductors, and AI.
Design Verification Engineer @ NVIDIA
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"When something is important, you do it even if the odds are not in your favor." ‑ Elon Musk
"When something is important, you do it even if the odds are not in your favor." ‑ Elon Musk
"The best way to predict the future is to invent it." ‑ Jensen Huang
"The best way to predict the future is to invent it." ‑ Jensen Huang
"Success is not an accident; success is a choice." - Stephen Curry
"Success is not an accident; success is a choice." - Stephen Curry
Research Area
Research Area
TBD
TBD
Else
Experience
Experience
NVIDIA, Design Verification Engineer (2025/04~Now)
NVIDIA, Design Verification Engineer (2025/04~Now)
SystemVerilog, UVM, GPU, Tegra, Display, Audio, HDMI, DP, PCIe, AXI, APB, CUDA, AI Algorithms
Development of UVM-based Testbench for GPU and Tegra Display/Audio subsystems
Coverage improvement and functional verification for multimedia interfaces including HDMI and DisplayPort
Implementation of AI Agent-based workflow to enhance verification efficiency and automation
Active participation in internal AI study groups, focusing on foundational and cutting-edge deep learning algorithms
Involved in GPU architecture research forums, exploring future design paradigms and performance optimization strategies
VICI Holdings, FPGA Engineer (2024/09~2025/02)
VICI Holdings, FPGA Engineer (2024/09~2025/02)
Altera FPGA, Quartus, Xilinx FPGA, Vivado, Verilog, Systemverilog, Peryl, Exchange API, Digital Design, Design Verification, C/C++
Implementation of Low-Latency Trading Infrastructure based on FPGA and high performance software, reducing execution time by 50%
Low-Latency DDR4 and HBM Memory Controller realization
Utilizing PCIe to complete a high-speed trading system
Construction of high performance trading strategy and risk control algorithm
MediaTek, Summer Intern (2024/07~2024/08)
MediaTek, Summer Intern (2024/07~2024/08)
Custom Compiler, Virtuoso, Peryl, Python, XML, Verilog, Verilog-AMS, HSPICE
TDC for SRAM readout speed measurement in 2nm process using gain calibration technique
Low Power and high performance SRAM circuit Design
Automatic testing for SRAM using SPICE, Peryl, and script
WorldQuant, WorldQuant Research Consultant (2023/09~now)
WorldQuant, WorldQuant Research Consultant (2023/09~now)
Quantization Trading, Alpha Strategy, Automated trading, High Frequency Trading
Develop Diverse Alpha Analyze, and Optimize for Performance
WorldQuant Research Consultant for Advanced Alpha analysis
Taiwan Electronic System Design Automation (TESDA) Silicon Engineer (2023/06~2024/06)
Taiwan Electronic System Design Automation (TESDA) Silicon Engineer (2023/06~2024/06)
UVM, Test Plan, Design Verfication, Computer Architecture, Compiler Design, RISCV, DLA, GPU, AHB, AXI, PCIe, MIPI, DDR5
ESL and DFT Design, RISC-V CPU and SoC Design Verification
NPU, APU and Deep Learning Accelerator(DLA) Development and Verification
AMBA Protocol and SPI, UART, I2C, JTAG, PCIe, MIPI, UCIe and DDR5
IP-XACT, Parser, Compiler and algorithm design
Industrial Technology Research Institute (ITRI)(2023/05~2022/06)
Industrial Technology Research Institute (ITRI)(2023/05~2022/06)
Python, Pytorch, Tensorflow, Machine Learning, Deep Learning
Use Deep Learning technique to realize face and commodity detection
Image recognition to fulfill the unmanned store
Richtek Summer Internship (2022/07~2022/08)
Richtek Summer Internship (2022/07~2022/08)
HSPICE, Finesim, Virtuoso, Spectre, Oscilloscope, Hall Transducer
Two-stage OP, Folded-cascoded OP, LDO analysis and simulation with advanced process
Oscillator and bandgap reference circuit analysis
Project
Project
Hardware Product Sprint, Google(2024/07~2024/08)
Hardware Product Sprint, Google(2024/07~2024/08)
Raspberry Pi, Hardware and Software Architecture Design, Keysight Recognition, Database Usage, React Native, Expo, LLM Utilization and Prompt, Python, Machine Learning
A smart refrigerator management system that helps users conveniently manage the food inside their fridge
Expiration date prediction by computer vision technique, Gas sensor, and Gemini utilization
Object recognition using FLANN-based, KNN matching, and brute force matching
Frontend app design and implementation with backend database integration
All Digital Phase-Locked Loop Program Research, Novatek(2022/09~2024/08)
All Digital Phase-Locked Loop Program Research, Novatek(2022/09~2024/08)
Mix-Signal Circuit, Analog to Digital Converter(ADC), PLL, PCB Design, DSP, DSM, Physical Design, System Design
-100dBc/Hz in-band noise and 3ps phase jitter fast-locking all digital fractional-N PLL at 6GHz with 90nm process
Innovative TDC with SAR-ADC to realize 0.5ps resolution differentiation
DSM and high-speed MMDIV(construct with TSPC) quantization noise cancellation with digital-to-time converter
High frequency and 16-bit DCO realization with DSM technique
Contact Information
Contact Information
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